"We really need to launch the smartphone quickly." Han Qingbo said in a deep voice.

Even though he is a technical talent, he also has some experience in business.

...

at the same time.

Motorola's smartphone leaked on the internet.

This smartphone launched by Motorola adopts a straight touch screen design.

The fuselage is divided into upper and lower layers.

The upper layer is a 3.7-inch screen with a resolution of 365x648 pixels. This screen is provided by Shanxing Technology.

This screen is a weakened version of the Retina technology derived from Shanxing.

Sliding out from the lower layer of the fuselage is a qwerty keyboard.

This Motorola design is very technological, but this design also brings a fatal problem.

That is, the battery of this mobile phone is only 2300 mAh, which is one-third less than other smartphones.

This also makes Milestone’s battery life one-third shorter than other phones.

However, if used normally, there is no big problem with eight hours of battery life.

...

What was subsequently exposed was the Sony Ericsson mobile phone.

This phone has a straight design with a 3.2-inch LCD screen and three physical buttons at the bottom of the screen.

The three buttons are return, main menu, and exit.

In terms of design, this phone is very close to the Kirin phone.

Early Android phones were designed this way.

...

Because other brands did not receive technical support, they launched smartphones powered by sj003.

However, sj003 can only use the simplified version of Pangu system, and the applications of the simplified version of Pangu system are very rare.

The current situation of sj003 is just like when Symbian mobile phone came out.

Fortunately, sj003 supports Kirin Universe and Kirin Payment System, and the performance of sj003 is several times faster than the newly released Symbian system.

Otherwise, no one might buy a mobile phone using this chip.

In addition to the sj003 mobile phone, these platforms have also launched many feature phones, and the market for feature phones is still very broad.

Netizens are dazzled by the indiscriminate bombardment of major mobile phone advertisements.

...

Beijing.

Building 8, Zhongguancun Science and Technology Park.

When you walk into the building from the door, you can see a large billboard.

Qiankun Chip Technology Manufacturing Co., Ltd. is printed on the billboard.

Nine small domestic mobile phone manufacturers are small shareholders of this company.

That's right, I'm talking about small shareholders.

Because the shareholdings of these nine companies are very small, Shunwei Capital holds the largest share of Qiankun Chip.

It's Rebus's position capital.

Originally, Qiankun Chip was an alliance composed of nine domestic no-name mobile phone companies.

Introduced by the owner of Red Hot Chili Pepper Mobile, Rebus joined the alliance and became its leader.

The reason why Red Hot Chili Pepper Mobile introduced Rebus to the alliance is because Rebus is a shareholder of Red Hot Chili Pepper.

After joining the alliance, Rebus also became a shareholder of various allies one after another.

Rebus naturally became the leader of this mobile phone alliance.

2nd floor.

Qiankun chip R&D room.

Rebus crossed his arms and appeared in the center of the office. In front of him was a 70-inch large screen.

Below the screen is a Kirin workstation specially used for chip simulation testing.

The workstation is connected to an overhead projector.

An engineer will operate the mouse to retrieve the CPU design file from the server.

"The pre-simulation of the CPU is now ready.

The simulation starts." After the engineer finished speaking, he pressed the Enter key on the keyboard.

A complete circuit design must include pre-simulation and post-simulation, both of which are necessary parts of verification.

Especially in complex chip designs, verification takes up 60%-70% of the entire chip design process time.

The purpose is to fully verify the chip functions as much as possible, expose problems as early as possible, and solve problems to ensure that all functions are completely correct.

Both pre-simulation and post-simulation belong to the scope of work of digital verification engineers, and both involve the establishment of a verification environment, which requires a lot of time.

Pre-simulation can also be called functional simulation and behavioral simulation. It mainly verifies whether the behavior of the circuit in an ideal environment is consistent with the design concept, and whether the circuit function meets the spec and design requirements.

Post-simulation can also be called timing simulation. Post-placement and routing simulation mainly focuses on the netlist after placement and routing, adding timing analysis to simulate and verify the correctness of the function.

The pre-simulation mainly verifies the functional correctness, and the post-simulation mainly verifies the timing correctness.

The previous simulation was concerned with device parameters, without considering circuit gate delays and line delays. There was no actual delay information about the internal logic units and connections of the device, and it was only a preliminary verification of the logic function of the system.

In addition to caring about device parameters, post-simulation also needs to consider line parasitic issues, which is why parasitic parameter extraction is required in the back-end link.

Because of the resistance of the wire itself, the mutual inductance between adjacent wires, and the coupling capacitance, signal noise, crosstalk, and reflection will occur inside the chip.

These effects can cause signal integrity problems, causing signal voltage fluctuations and changes, and if severe, can lead to signal distortion errors.

Therefore, it is very important to extract parasitic parameters for re-analysis and verification, and to analyze signal integrity issues.

A more obvious distinguishing mark is layout and routing.

Pre-simulation needs to be carried out during the rtl code design phase, and post-simulation must be carried out after the placement and routing phase.

After layout and wiring, the specific shapes, sizes, and mutual positions of various devices such as transistors have been determined, which means that the structure of the chip that will be manufactured in the future has also been determined.

Different layout designs will produce different parasitic parameters.

For example, the size of the distributed capacitance generated between the metal interconnection lines and the substrate is closely related to the layout design. Different layout designs may have different line lengths and paths, and thus different parasitic capacitances.

Other parasitic situations are similar to this, and most of them are related to the specific territory.

Pre-simulation mainly analyzes the circuit logic function and is faster than post-simulation.

Post-simulation introduces the actual circuit of parasitic distribution parameters for simulation, which can better reflect the actual working conditions of the chip and is closer to the actual simulation, but it takes relatively longer time.

Sometimes the simulation results before and after are inconsistent or even very different. In fact, a large part of the reason is that their respective focuses are different.

Before the emergence of Kirin EDA and Kirin workstation, it would take seven or eight hours to do a front-to-back simulation of a chip.

But after these two things appeared, it only took an hour to do a chip simulation.

This is why Mike Clark said that Kirin EDA will greatly improve the efficiency of their chip design.

It takes seven or eight hours to verify whether there is a problem with a chip design.

Engineers can only wait quietly for the results before they come out, but there are only eight hours a day.

Can such verification efficiency not be slow when developing chips?

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